feat: microarch-aware optimizer, native f16, and et-soc tensor codegen #1

Merged

RossComputerGuy merged 2 commits from uarch-opt into master

2026-07-18 02:51:38 +00:00

RossComputerGuy commented

2026-07-18 00:17:07 +00:00

(Migrated from github.com)

Adds three large, independently-useful capabilities plus the backend work they required. All new paths are gated, so existing targets are byte-identical when the features are off.

Microarchitecture-aware optimizer (libs/vulcan-opt/microarch/)

Per-model machine description: instruction latency and throughput, issue ports and execution units, fetch alignment, macro-op fusion pairs, and ISA feature flags, with a registry of predefined models (Ampere Altra / Neoverse N1, ET-SOC, River) and host detection.
Model-driven passes behind a single microarch.optimize entry: instruction scheduling, loop unrolling, SLP vectorization, prefetch insertion, and loop-header alignment.
A cost model that answers "when to vectorize": scalar-vs-vector profitability, per-type throughput, result-chaining credit, and contiguous load and store coalescing.
INT8 dot-product (SDOT/UDOT) recognition, and vulcan-uarch-bench, a JIT gain-measurement tool (perf counters on Linux, wall-clock fallback else).

Native f16 (half-precision) across the IR and every backend

The IR FloatKind gains f16, across types, bitcode, verify, and float-to-float convert.
aarch64 (base-ISA fcvt emulation plus native FEAT_FP16), riscv64 (branchless software conversion plus native Zfh), wasm (software), x86_64 (F16C), c (_Float16), js (Math.f16round), and SPIR-V (Float16 capability).
Native per-backend paths are model-gated, and the emulation fallback is byte-identical when the feature is off. Backends that cannot do f16 reject it cleanly rather than miscompiling.

ET-SOC tensor unit (matmul)

MatMul IR op over fp32, fp16, int8, and uint8, with mixed operand signedness, K-tiling, an optional int8-requantize epilogue (per-column scale, bias, zero-point, relu, int8 or uint8 output), C-memory accumulation, and a self-contained embedded lowering for use mid-function.
riscv64 lowering over the CSR tensor protocol, plus et-soc VPU SLP vectorization with packed-single and packed-integer ops and fmadd.ps FMA.
Automatic recognition of naive triply-nested matmul loops into the MatMul op, in whole-function, non-whole-function (region-gated, embedded), and memory-accumulator forms.

Backend and codegen improvements

riscv64 integer, float, and vector block-param spill, reachability-aware instruction selection, branch relaxation, Zicbop prefetch, and a parallel-move permutation-cycle fix.
FMA contraction (a*b+c into one single-rounding op), scalar and vector, on aarch64 (FMLA/FMLS) and riscv64 (vfmacc/vfmsac/vfnmsac, et-soc fmadd.ps).

Validation: differential-tested on real aarch64 hardware, riscv64 under qemu, and the ET-SOC sw-sysemu interpreter, with correctness asserted bit-for-bit against independent scalar references. sw-sysemu is packaged and wired into the Nix check so the et-soc tests run under nix flake check.

Adds three large, independently-useful capabilities plus the backend work they required. All new paths are gated, so existing targets are byte-identical when the features are off. Microarchitecture-aware optimizer (libs/vulcan-opt/microarch/) - Per-model machine description: instruction latency and throughput, issue ports and execution units, fetch alignment, macro-op fusion pairs, and ISA feature flags, with a registry of predefined models (Ampere Altra / Neoverse N1, ET-SOC, River) and host detection. - Model-driven passes behind a single microarch.optimize entry: instruction scheduling, loop unrolling, SLP vectorization, prefetch insertion, and loop-header alignment. - A cost model that answers "when to vectorize": scalar-vs-vector profitability, per-type throughput, result-chaining credit, and contiguous load and store coalescing. - INT8 dot-product (SDOT/UDOT) recognition, and vulcan-uarch-bench, a JIT gain-measurement tool (perf counters on Linux, wall-clock fallback else). Native f16 (half-precision) across the IR and every backend - The IR FloatKind gains f16, across types, bitcode, verify, and float-to-float convert. - aarch64 (base-ISA fcvt emulation plus native FEAT_FP16), riscv64 (branchless software conversion plus native Zfh), wasm (software), x86_64 (F16C), c (_Float16), js (Math.f16round), and SPIR-V (Float16 capability). - Native per-backend paths are model-gated, and the emulation fallback is byte-identical when the feature is off. Backends that cannot do f16 reject it cleanly rather than miscompiling. ET-SOC tensor unit (matmul) - MatMul IR op over fp32, fp16, int8, and uint8, with mixed operand signedness, K-tiling, an optional int8-requantize epilogue (per-column scale, bias, zero-point, relu, int8 or uint8 output), C-memory accumulation, and a self-contained embedded lowering for use mid-function. - riscv64 lowering over the CSR tensor protocol, plus et-soc VPU SLP vectorization with packed-single and packed-integer ops and fmadd.ps FMA. - Automatic recognition of naive triply-nested matmul loops into the MatMul op, in whole-function, non-whole-function (region-gated, embedded), and memory-accumulator forms. Backend and codegen improvements - riscv64 integer, float, and vector block-param spill, reachability-aware instruction selection, branch relaxation, Zicbop prefetch, and a parallel-move permutation-cycle fix. - FMA contraction (a*b+c into one single-rounding op), scalar and vector, on aarch64 (FMLA/FMLS) and riscv64 (vfmacc/vfmsac/vfnmsac, et-soc fmadd.ps). Validation: differential-tested on real aarch64 hardware, riscv64 under qemu, and the ET-SOC sw-sysemu interpreter, with correctness asserted bit-for-bit against independent scalar references. sw-sysemu is packaged and wired into the Nix check so the et-soc tests run under nix flake check.