LilithSemi/river
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Modular RISC-V implementation & SoC
82 commits 1 branch 0 tags 1.3 MiB
  • Dart 98.3%
  • Nix 1.6%
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Tristan Ross 0a61520e48 refactor: booting linux
2026-08-29 20:38:46 +00:00
.github/workflows feat(river_hdl): adding microcode execution (#1) 2026-01-19 02:52:51 +00:00
docs refactor: use harbor 2026-07-28 05:55:29 +00:00
nix refactor: booting linux 2026-08-29 20:38:46 +00:00
packages refactor: booting linux 2026-08-29 20:38:46 +00:00
pkgs refactor: booting linux 2026-08-29 20:38:46 +00:00
.envrc fix(river_hdl): 64-bit tests 2025-12-31 19:16:40 -08:00
.gitignore refactor: booting linux 2026-08-29 20:38:46 +00:00
analysis_options.yaml refactor: use harbor 2026-07-28 05:55:29 +00:00
devices.nix refactor: booting linux 2026-08-29 20:38:46 +00:00
flake.lock refactor: booting linux 2026-08-29 20:38:46 +00:00
flake.nix refactor: booting linux 2026-08-29 20:38:46 +00:00
LICENSE refactor: use harbor 2026-07-28 05:55:29 +00:00
pubspec.lock refactor: booting linux 2026-08-29 20:38:46 +00:00
pubspec.lock.json refactor: booting linux 2026-08-29 20:38:46 +00:00
pubspec.yaml refactor: booting linux 2026-08-29 20:38:46 +00:00
README.md feat: init readme 2025-11-25 20:35:12 -08:00
treefmt.nix feat: init 2025-11-17 10:34:06 -08:00

README.md

River

River is an open source & modular RISC-V based CPU & SoC.